Dimensions of the high speed CMOS gate length including polysilicon gate thickness scales in line with the reducing lithography node. Generic CMOS processes that have transistors optimized for the high speed Vcc operation and the slightly higher voltage I/O typically use a single polysilicon gate thickness. The Flash process, however, requires a discrete set of transistors for the core cell (non-volatile memory cells), as well as high speed CMOS (Vcc) and high voltage circuitry. Different types of transistors have different functions, and thus have different preferred dimensions.
Furthermore, an increasing number of semiconductor integrated circuits containing a non-volatile memory cell array and logic circuits are in demand due to the enhanced value provided. The transistors of a non-volatile memory cell array may have a stacked gate structure. The peripheral circuits for a non-volatile memory cell array may include high breakdown voltage transistors that have a drive circuit which handles high voltages (program/erasure, etc.) required for driving the memory cells. The peripheral circuits may also include a low voltage transistor circuit to perform logical functions and data manipulation at high speeds.
The manufacturing processes of different types of transistors are different and therefore may have poor compatibility. Therefore, this type of non-volatile semiconductor memory device gives rise to a great increase in number of steps and costs if it is to be integrated in the same semiconductor chip together with a peripheral logic circuit such as a CPU or an MPU.